VLSI implementation of reduced complexity wallace multiplier using energy efficient CMOS full adder

A multiplier is one of the important hardware blocks in most digital and high performance systems such as microprocessors, FIR filter and digital signal processors etc. With improving in technology, many researchers have tried and are trying to design multipliers which offer high speed, low power consumption and less area. However area and speed are two most important constraints. So improving speed results always in larger area. So here we try to find out the best solution among the both of them. In order to reduce the hardware which ultimately reduces an area and power, Energy Efficient full adders plays an important role in Wallace tree multiplier. Reduced Complexity Wallace multiplier (RCWM) will have fewer adders than Standard Wallace multiplier (SWM). A Reduced Complexity Wallace multiplier presented in this paper is having the same delay as that of Standard Wallace multipliers. In both multipliers, at the last stage Carry Propagating Adder (CPA) is used. This paper proposes use of Energy Efficient CMOS full adder in reduced complexity Wallace Multiplier at the place of Full adder of standard Wallace Multiplier in order to reduce Area, Power and improvement in speed. The Reduced complexity reduction method smartly reduces the number of half adders with 70-80% reduction in an area of half adders than standard Wallace multipliers.