DocumentCode :
3077451
Title :
Pipelined cordic architectures for fast VLSI filtering and array processing
Author :
Deprettere, Ed F. ; Dewilde, P. ; Udo, R.
Author_Institution :
Delft Universtiy of Technology, Delft, The Netherlands
Volume :
9
fYear :
1984
fDate :
30742
Firstpage :
250
Lastpage :
253
Abstract :
The paper presents a revised functional description of Volder´s Coordinate Rotation Digital Computer algorithm (CORDIC), as well as allied VLSI implementable processor architectures. Both pipelined and sequential structures are considered. In the general purpose or multi-function case, pipeline length (number of cycles), function evaluation time and accuracy are all independent of the various executable functions. High regularity and minimality of data-paths, simplicity of control circuits and enhancement of function evaluation speed are ensured, partly by mapping a unified set of micro-operations, and partly by invoking a natural encoding of the angle parameters. The approach benefits the execution speed in array configurations, since it will allow pipelining at the bit level, thereby providing fast VLSI implementations of certain algorithms exhibiting substantial structural pipelining or parallelism.
Keywords :
Algorithm design and analysis; Array signal processing; Circuits; Computer architecture; Filtering; Paper technology; Pipeline processing; Signal processing algorithms; Vectors; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '84.
Type :
conf
DOI :
10.1109/ICASSP.1984.1172772
Filename :
1172772
Link To Document :
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