Title :
A 640 MB/s bi-directional data strobed, double-data-rate SDRAM with a 40 mW DLL circuit for a 256 MB memory system
Author :
Kim, C. ; Lee, J. ; Lee, Jeyull ; Kim, Bumki ; Park, C. ; Lee, Sang-Rim ; Lee, Sang-Rim ; Park, C. ; Roh, J. ; Nam, H. ; Kim, Dongkyu ; Jung, T. ; Cho, S.
Author_Institution :
Samsung Electron. Co. Ltd., Kyungki, South Korea
Abstract :
In a memory system employing wide channel high-performance DRAMs, skews resulting from nonideal system and chip environments become the most critical factor. This 256 MB memory system achieves 256 Gb/s peak bandwidth with a 160 MHz clock and 64b channel using a /spl plusmn/0.4 V-swing, push-pull type I/O interface (SSTL).
Keywords :
DRAM chips; 160 MHz; 256 MB; 40 mW; 640 MB/s; access time; bi-directional data; bidirectional data strobed double-data rate scheme; chip environments; chip size overhead; clock-to-I/0 data skews; data path loading difference; double-data-rate SDRAM; flight-time dependent skews; high-performance DRAMs; locking frequency; low-power DLL circuit; memory system; nonideal system; peak bandwidth; prefetch operation; push-pull type I/O interface; twisted data bus architecture; Bandwidth; Bidirectional control; Boolean functions; Circuits; Clocks; Data structures; Delay; Frequency; Prefetching; SDRAM;
Conference_Titel :
Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-4344-1
DOI :
10.1109/ISSCC.1998.672415
