Title :
Source synchronization and timing Vernier techniques for 1.2 GB/s SLDRAM interface
Author :
Morooka, Y. ; Nakase, Y. ; Choi, J.-M. ; Shin, H.J. ; Perlman, D.J. ; Kolor, D.J. ; Yoshimura, T. ; Watanabe, N. ; Matsuda, Y. ; Kumanoya, M. ; Yamada, M.
Author_Institution :
Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
SLDRAM architecture is a proposed standard for high bandwidth, high-speed packetized DRAM. Its I/O interface, SLDRAM interface, is specified for high-speed command/address and data transfers between an SLDRAM controller and SLDRAMs. The SLDRAM interface is demonstrated through a setup involving an experimental chip and an emulation motherboard mounting several SLDRAM emulation modules. The experimental chip is packaged and mounted on a conventional PCB module. The interface of the chip operates up to 600 Mb/s per pin with a 300 MHz clock.
Keywords :
synchronisation; 1.2 GB/s; 300 MHz; PCB module; SLDRAM architecture; SLDRAM interface; emulation motherboard; high-speed command/address transfers; high-speed packetized DRAM; source synchronization; standard; timing Vernier techniques; Calibration; Circuit testing; Clocks; Delay; Emulation; Packaging; Pins; Synchronization; Timing; Topology;
Conference_Titel :
Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-4344-1
DOI :
10.1109/ISSCC.1998.672416
