Author :
Lau, B. ; Chan, Y.-F. ; Moncayo, A. ; Ho, J. ; Allen, M. ; Salmon, J. ; Liu, J. ; Muthal, M. ; Lee, C. ; Nguyen, T. ; Horine, B. ; Leddige, M. ; Huang, K. ; Wei, J. ; Yu, L. ; Tarver, R. ; Hsia, Y. ; Vu, R. ; Tsern, E. ; Liaw, H.-J. ; Hudson, J. ; Nguyen,
Author_Institution :
Rambus, Mountain View, CA, USA
Abstract :
A high-speed interface cell delivers 800 Mb/s/pin data transfer rate on a 26b wide I/O interface consisting of a dual-byte data field and a byte-wide command field. For 2.6 GB/s data rate, a 400 MHz clock recovery circuit guarantees the timing margin for transferring 800 mV swing data at both clock edges over the I/O interface. Data from the high speed interface is internally deserialized to provide a 100 MHz (f/4) ASIC clock interface. A test chip contains three megacells and built-in clock synchronization circuits to ensure proper data transfer between the three megacells with minimal impact on latency. Controlled impedance buses, referred to as channels, with careful PCB layout ensure 800 Mb/s/pin data rate on-board for ASIC-to-ASIC or ASIC-to-DRAM system configuration.
Keywords :
timing; 2.6 GB/s; 400 MHz; 800 mV; ASIC-to-ASIC system configuration; ASIC-to-DRAM system configuration; I/O interface; built-in clock synchronization; byte-wide command field; clock edges; clock recovery circuit; controlled impedance buses; data transfer rate; dual-byte data field; high speed interface; latency; megacells; multi-purpose chip-to-chip interface; timing margin; Circuit simulation; Clocks; Current control; Decoding; Frequency; Logic; Prototypes; Semiconductor device measurement; Solid modeling; Solid state circuits;
