Title :
A power efficient carry save adder and modified carry save adder using CMOS technology
Author :
Mahalakshmi, R. ; Sasilatha, T.
Author_Institution :
Anna Univ., Chennai, India
Abstract :
Adders form an almost obligatory component of every contemporary integrated circuit. The primary requirement of the adder is that it is fast and efficient in terms of power consumption and chip area. In this paper we design a CMOS Logic based Carry Save adder and Modified carry save adder and to deliver with 250 nm, 65nm technology with low power by replacing the architecture for minimal power utilization.
Keywords :
CMOS logic circuits; adders; integrated circuit design; logic design; low-power electronics; CMOS logic based carry save adder; CMOS technology; chip area; modified carry save adder; power consumption; power efficient carry save adder; Adders; CMOS integrated circuits; Computational intelligence; Conferences; Educational institutions; Power demand; Propagation delay; CPA-Carry Propagate Addition; CSA-Carry Save Adder; LUT-Look Up Table; MCSA-Modified Carry Save Adder; RCA-Ripple Carry Adder;
Conference_Titel :
Computational Intelligence and Computing Research (ICCIC), 2013 IEEE International Conference on
Conference_Location :
Enathi
Print_ISBN :
978-1-4799-1594-1
DOI :
10.1109/ICCIC.2013.6724189
