Efficient design of symbol detector for MIMO-OFDM based wireless LANs

Author

Noh, Seungpyo ; Jung, Yunho ; Kim, Jaeseok

Author_Institution

Dept. of Electr. & Electr. Eng., Yonsei Univ., Seoul, South Korea

fYear

2005

fDate

2-4 Nov. 2005

Firstpage

25

Lastpage

29

Abstract

In this paper, efficient hardware architecture for MIMO-OFDM symbol detector with two transmit and two receive antennas is proposed. The proposed symbol detector supports two MIMO-OFDM modes of SFBC-OFDM and SDM-OFDM. It can be implemented with shared-architecture, since the detection algorithms of two MIMO-OFDM modes are similar. Therefore, by eliminating duplicated function blocks, reduced-complexity implementation can be possible. It was designed in a hardware description language and synthesized to gate-level circuits using 0.18 μm CMOS standard cell library. The total logic gate count for the symbol detector is 164K. By the efficient hardware architecture, the proposed symbol detector results in the reduction of the logic gates by 34% and the power consumption by 38%.

Keywords

CMOS integrated circuits; MIMO systems; OFDM modulation; antenna arrays; hardware description languages; integrated circuit design; wireless LAN; 0.18 mum; CMOS standard cell library; MIMO-OFDM; gate-level circuits; hardware architecture; hardware description language; receive antennas; symbol detector; transmit antennas; wireless LAN; CMOS logic circuits; Circuit synthesis; Detection algorithms; Detectors; Energy consumption; Hardware design languages; Libraries; Logic gates; Receiving antennas; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems Design and Implementation, 2005. IEEE Workshop on

ISSN

1520-6130

Print_ISBN

0-7803-9333-3

Type

conf

DOI

10.1109/SIPS.2005.1579833

Filename

1579833