Title :
A Class of Low Power Error Compensation Iterative Decoders
Author :
Hussien, Amr M A ; Khairy, Muhammad S. ; Khajeh, Amin ; Eltawil, Ahmed M. ; Kurdahi, Fadi J.
Author_Institution :
Univ. of California Irvine, Irvine, CA, USA
Abstract :
Recent power reduction techniques aggressively modulate the supply voltage of embedded buffering memories allowing acceptable hardware errors to flow through the processing chain. In this paper, we introduce a class of modified Turbo and LDPC decoders that provide significant improvements over standard decoders in the presence of hardware noise. Simulation results show a consistent improvement in the BER performance of the modified decoders across all SNRs with very small area and power overheads as compared to the conventional decoders.
Keywords :
error compensation; iterative decoding; low-power electronics; parity check codes; turbo codes; LDPC decoders; embedded buffering memories; low power error compensation iterative decoders; turbo decoders; Decoding; Hardware; Measurement; Parity check codes; Peer to peer computing; Signal to noise ratio;
Conference_Titel :
Global Telecommunications Conference (GLOBECOM 2011), 2011 IEEE
Conference_Location :
Houston, TX, USA
Print_ISBN :
978-1-4244-9266-4
Electronic_ISBN :
1930-529X
DOI :
10.1109/GLOCOM.2011.6134075
