• DocumentCode
    3078833
  • Title

    A cost-effective demosaicked image enhancement for a single chip CMOS image sensor

  • Author

    Lee, Wonjae ; Kim, Jaeseok

  • Author_Institution
    Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea
  • fYear
    2005
  • fDate
    2-4 Nov. 2005
  • Firstpage
    148
  • Lastpage
    153
  • Abstract
    A cost-effective demosaicked image enhancement method for a single chip CMOS (complementary metal oxide semiconductor) image sensor which has on-chip ISP (image signal processor) is introduced. CMOS image sensors are becoming popular, because various circuits can be integrated with it into a single chip. In a single chip CMOS image sensor for handheld devices which requires low power consumption, ISP has to be implemented to small size while maintaining the high performance. Demosaicking and image enhancing are the largest blocks in the ISP, because they need some line memories. In this paper, we propose a new method to minimize the number of line memory. In the proposed method, contrast enhancement is done using the buffered data for demosaicking. The green channel is used instead of luminance. Experimental results indicate that the proposed approach enhances the image quality without additional line memories. The proposed method is implemented on FPGA chip in real time mode, and performed successfully.
  • Keywords
    CMOS image sensors; brightness; field programmable gate arrays; image enhancement; image resolution; image segmentation; FPGA chip; complementary metal oxide semiconductor; contrast enhancement; cost-effective demosaicked image enhancement; green channel; handheld devices; image sensor; image signal processor; low power consumption; luminance; onchip ISP; single chip CMOS; CMOS image sensors; CMOS process; Circuits; Energy consumption; Field programmable gate arrays; Handheld computers; Image enhancement; Image quality; Image sensors; Signal processing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signal Processing Systems Design and Implementation, 2005. IEEE Workshop on
  • ISSN
    1520-6130
  • Print_ISBN
    0-7803-9333-3
  • Type

    conf

  • DOI
    10.1109/SIPS.2005.1579855
  • Filename
    1579855