A 32×32 smart photo-array with minimum-size FGMOS for amplification and FPN reduction

A logarithmic response photoarray, incorporating two minimum-sized floating-gate MOSFETs (FGMOS) in its basic photocell, is presented. Exploiting the same FGMOS as an analog memory element for fixed pattern noise (FPN) reduction, and as an inherent amplifying element, is, to our knowledge, novel. The above features, favored by the use of small control gate capacitors, lead to area reduction. The circuit behavior is analyzed and experimental results of a 32×32 prototype array implemented in AMS 0.6μm CMOS technology, are presented and discussed.