A hardware accelerator for H.264/AVC motion compensation

Author

Tseng, Huang-Chun ; Chang, Cheng-Ru ; Lin, Youn-Long

Author_Institution

Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan

fYear

2005

fDate

2-4 Nov. 2005

Firstpage

214

Lastpage

219

Abstract

We propose a hardware accelerator for H.264/AVC motion compensation. Our design supports all advanced features including variable-block-size motion estimation from multiple reference frames for both P and B slices, quarter-pixel accuracy, and weighted bi-directional prediction. We pay special attention to memory subsystem design for optimizing both memory usage and memory bandwidth. We have integrated the accelerator into an H.264/AVC main profile decoder in FPGA prototype. Compared with previous work, our accelerator is smaller and faster.

Keywords

field programmable gate arrays; image resolution; motion compensation; motion estimation; video coding; B slices; FPGA prototype; H.264/AVC; P slices; hardware accelerator; memory bandwidth; memory subsystem; memory usage; motion compensation; multiple reference frames; profile decoder; quarter-pixel accuracy; variable-block-size motion estimation; weighted bi-directional prediction; Automatic voltage control; Bandwidth; Bidirectional control; Decoding; Design optimization; Field programmable gate arrays; Hardware; Motion compensation; Motion estimation; Prototypes;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems Design and Implementation, 2005. IEEE Workshop on

ISSN

1520-6130

Print_ISBN

0-7803-9333-3

Type

conf

DOI

10.1109/SIPS.2005.1579867

Filename

1579867