Title :
A BIST scheme based on self-nonself discrimination of immune system
Author :
de Souza, C.P. ; Freire, R.C.S. ; de Assis, F.M.
Author_Institution :
Dept. of Electr. Eng., Campina Grande Federal Univ.
fDate :
Sept. 29 2004-Oct. 1 2004
Abstract :
Built-in self-test (BIST) techniques are rapidly becoming an industry-wide standard test technique in the design of testing support hardware for VLSI circuits. In the BIST setup both test pattern generation and output response analysis are performed on-chip hardware. In this manuscript a BIST scheme based on immune system is presented. The main conceptual ingredient utilized in order to build the proposed scheme is the application of the negative-selection mechanism of the immune system, which is able to discriminate between the self (body´s own cell) and any foreign cell (non-self). Experimental results concerning fault detection in some ISCAS85 benchmarks circuits are presented
Keywords :
VLSI; built-in self test; fault tolerance; BIST scheme; VLSI circuit; built-in self-test technique; fault detection; fault tolerance; immune system; industry-wide standard test technique; negative-selection mechanism; output response analysis; self-nonself discrimination; test pattern generation; testing support hardware; Automatic testing; Built-in self-test; Circuit testing; Hardware; Immune system; Pattern analysis; Performance analysis; Performance evaluation; Test pattern generators; Very large scale integration;
Conference_Titel :
Machine Learning for Signal Processing, 2004. Proceedings of the 2004 14th IEEE Signal Processing Society Workshop
Conference_Location :
Sao Luis
Print_ISBN :
0-7803-8608-4
DOI :
10.1109/MLSP.2004.1423043