A multiseed counter TPG with performance guarantee

Several mechanisms based on ROMs, LFSRs, counters, cellular automata, have been proposed as built-in test pattern generators with trade-offs between hardware and time overhead. This paper presents and analyses a scheme based on a counter with multiple seeds to generate a test set with low hardware overhead. A fast CAD tool determines the number of clock cycles required for the test set generation and this number is shown to be close to the best possible. A comparison to other existing approaches on the ISCAS´85 benchmarks shows that the proposed mechanism can offer a favorable hardware/time overhead for many circuits