Custom Network on Chip architecture for map generation in autonomous navigating robots

In this paper, we propose a custom Network on Chip architecture for implementation of inter-processor communication in a multi-processor system on chip designed for implementation of mapping using data received through ultrasound sensors mounted on an autonomous robot. The latency problem associated with shared bus architecture and the need for a complex arbitration method is sought to be overcome through the proposed network. The multi-processor system has been implemented on Xilinx Virtex-5 FPGA and we propose a network on chip architecture to provide interface to the Fast simplex Link Bus for communicating with soft-core processors integrated on chip. We compare the performance of the shared bus architecture with that of the proposed custom Network on chip architecture to illustrate the advantage offered by the proposed architecture.