DocumentCode :
3079466
Title :
A shared-variable-based synchronization approach to efficient cache coherence simulation for multi-core systems
Author :
Fu, Cheng-Yang ; Wu, Meng-Huan ; Tsay, Ren-Song
Author_Institution :
Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fYear :
2011
fDate :
14-18 March 2011
Firstpage :
1
Lastpage :
6
Abstract :
This paper proposes a shared-variable-based approach for fast and accurate multi-core cache coherence simulation. While the intuitive, conventional approach - synchronizing at either every cycle or memory access - gives accurate simulation results, it has poor performance due to huge simulation overloads. We observe that timing synchronization is only needed before shared variable accesses in order to maintain accuracy while improving the efficiency in the proposed shared-variable-based approach. The experimental results show that our approach performs 6 to 8 times faster than the memory-access-based approach and 18 to 44 times faster than the cycle-based approach while maintaining accuracy.
Keywords :
cache storage; multiprocessing systems; cycle-based approach; memory access; memory-access-based approach; multicore cache coherence simulation; multicore systems; shared variable access; shared-variable-based synchronization; timing synchronization; Accuracy; Coherence; Kernel; Simulation; Switches; Synchronization; cache-coherence; timing synchronization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011
Conference_Location :
Grenoble
ISSN :
1530-1591
Print_ISBN :
978-1-61284-208-0
Type :
conf
DOI :
10.1109/DATE.2011.5763061
Filename :
5763061
Link To Document :
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