DocumentCode :
3079518
Title :
Panel: Opportunities and pitfalls in HDL-based system design
Author :
Gupta, Rajesh K.
Author_Institution :
Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
fYear :
1996
fDate :
7-9 Oct 1996
Firstpage :
56
Lastpage :
57
Abstract :
This panel discusses the complexities of system designs using textual Hardware Description Languages (HDLs) such as Verilog and VHDL. As the proliferation of circuits and systems design using HDLs continues questions arise as to whether HDL-based programming provides any real productivity gains in the design of complex integrated hardware. Are there are any alternatives, such as graphical or visual formalisms that are perhaps better suited for the task? We start the discussion by examining the relevant features of today´s complex hardware systems and the requirements these impose on the modeling language and methodologies
Keywords :
hardware description languages; logic CAD; HDLs; VHDL; Verilog; hardware systems; modeling language; system designs; textual Hardware Description Languages; Broadcasting; Clocks; Design methodology; Discrete event simulation; Engines; Handicapped aids; Hardware design languages; Large-scale systems; Productivity; Virtual machining;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1996. ICCD '96. Proceedings., 1996 IEEE International Conference on
Conference_Location :
Austin, TX
ISSN :
1063-6404
Print_ISBN :
0-8186-7554-3
Type :
conf
DOI :
10.1109/ICCD.1996.563531
Filename :
563531
Link To Document :
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