A 1 mm 50 K-pixel IT CCD image sensor for miniature camera system

A 1 mm 50 k-pixel interline CCD features a 4/spl times/4 /spl mu/m/sup 2/ pixel, integration of a Vsub adjust circuit and a packageless assembly of a chip-provided microlens. The chip size and the assembled device outer sizes are 1.1 (H)/spl times/1.34 (V)mm/sup 2/ and 1.2 (H)/spl times/1.5 (V)mm/sup 2/ respectively. The 4/spl times/4 /spl mu/m/sup 2/-Pixel has image quality equivalent to that of conventional 5/spl times/5 /spl mu/m/sup 2/ pixel. Channel narrowing is important in design with small pixel size, because narrowed channel causes reduction of handling charge in the vertical CCD. A low-temperature oxidation process minimizes channel narrowing caused by lateral diffusion of boron. The thickness of the transfer gate oxide is reduced to 80%, which also results in an increase of handling charge. Tne creation of the p-well and n-type region of the photodiode (PD) are by high-energy ion implantation, making the isolation length between VCCD and PD shorter than that with the conventional method. Owing to the above techniques, VCCD with 0.8pm channel width has 2.0/spl times/10/sup 4/ electron/pixel handling charge.