Title :
Arithmetic pattern generators for built-in self-test
Author :
Stroele, Albrecht P.
Author_Institution :
Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
Abstract :
Adders, subtracters, ALUs, and multipliers, which are available in many data paths, can be utilized to generate test patterns for built-in self-test. In this paper guidelines for the design of arithmetic pattern generators are developed. Experimental results show that the generated patterns achieve similar fault coverage as pseudo-random sequences and require about the same test length. Hence, instead of adding LFSR-based test registers, arithmetic pattern generators can be used and performance degradation is avoided
Keywords :
adders; built-in self test; digital arithmetic; multiplying circuits; ALUs; LFSR-based test registers; adders; arithmetic pattern generators; built-in self-test; fault coverage; multipliers; performance degradation; pseudo-random sequences; subtracters; Adders; Arithmetic; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Clocks; Guidelines; Registers; Test pattern generators;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1996. ICCD '96. Proceedings., 1996 IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-7554-3
DOI :
10.1109/ICCD.1996.563545
