Arithmetic pattern generators for built-in self-test

Adders, subtracters, ALUs, and multipliers, which are available in many data paths, can be utilized to generate test patterns for built-in self-test. In this paper guidelines for the design of arithmetic pattern generators are developed. Experimental results show that the generated patterns achieve similar fault coverage as pseudo-random sequences and require about the same test length. Hence, instead of adding LFSR-based test registers, arithmetic pattern generators can be used and performance degradation is avoided