DocumentCode :
3079867
Title :
Dynamic write limited minimum operating voltage for nanoscale SRAMs
Author :
Nalam, Satyanand ; Chandra, Vikas ; Aitken, Robert C. ; Calhoun, Benton H.
Author_Institution :
Dept. of ECE, Univ. of Virginia, Charlottesville, VA, USA
fYear :
2011
fDate :
14-18 March 2011
Firstpage :
1
Lastpage :
6
Abstract :
Dynamic stability analysis for SRAM has been growing in importance with technology scaling. This paper analyzes dynamic writability for designing low voltage SRAM in nanoscale technologies. We propose a definition for dynamic write limited VMIN. To the best of our knowledge, this is the first definition of a VMIN based on dynamic stability. We show how this VMIN is affected by the array capacity, the voltage scaling of the word-line pulse, the bitcell parasitics, and the number of cycles prior to the first read access. We observe that the array can be either dynamically or statically write limited depending on the aforementioned factors. Finally, we look at how voltage-bias based write assist techniques affect the dynamic write limited VMIN.
Keywords :
SRAM chips; dynamic stability analysis; dynamic writability analysis; dynamic write limited minimum operating voltage; nanoscale SRAM; word-line pulse; Arrays; Capacitance; Measurement; Power system dynamics; Power system stability; Random access memory; Stability analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011
Conference_Location :
Grenoble
ISSN :
1530-1591
Print_ISBN :
978-1-61284-208-0
Type :
conf
DOI :
10.1109/DATE.2011.5763081
Filename :
5763081
Link To Document :
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