Title :
Developing an integrated verification and debug methodology
Author :
Matsuda, Akitoshi ; Ishihara, Tohru
Author_Institution :
Dept. of Automotive Sci., Kyushu Univ., Fukuoka, Japan
Abstract :
As design complexity of LSI systems increase, so does the verification challenges. It is very important, yet difficult to find all design errors and correct them in a timely manner. This paper presents our experience with a new verification and debug methodology based on the combination of formal verification and automated debugging. This methodology, which is applied to the development of a DDR2 memory design targeted for an FGPA, is found to significantly reduce the verification and debug tasks typically performed.
Keywords :
formal verification; large scale integration; program debugging; DDR2 memory design; FGPA; LSI systems; automated debugging; debug methodology; design complexity; formal verification; integrated verification; Analytical models; Computer bugs; Debugging; Field programmable gate arrays; Formal verification; Manuals; Radiation detectors; debug; methodology; system LSI; verification;
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011
Conference_Location :
Grenoble
Print_ISBN :
978-1-61284-208-0
DOI :
10.1109/DATE.2011.5763087