Title :
An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations
Author :
Eneman, G. ; Cho, J. ; Moroz, V. ; Milojevic, D. ; Choi, M. ; Meyer, K. De ; Mercha, A. ; Beyne, E. ; Hoffmann, T. ; Van der Plas, G.
Author_Institution :
ESAT-INSYS, K.U. Leuven, Leuven, Belgium
Abstract :
We present a compact model that provides a quick estimation of the stress and mobility patterns around arbitrary configurations of Through-Silicon Via´s (TSVs). No separate TCAD simulations are required for these configurations. It estimates nFET and pFET mobility for industry-standard as well as for (100)/<;100>; substrate orientations. As the model provides mobility info in less than 0.1 millisecond/transistor/TSV, it is possible to be used in combination with layouting tools and circuit simulators to optimise layouts of circuits for digital and analog applications. The model has been integrated into the 3D PathFinding flow, for steering 3D IO placement during stack definition.
Keywords :
circuit simulation; field effect transistors; integrated circuit layout; three-dimensional integrated circuits; 3D IO placement steering; 3D pathfinding flow; analog application; analytical compact model; circuit layout optimisation; circuit simulator; digital application; industry standard; layouting tool; mobility pattern; nFET; pFET mobility; stack definition; stress estimation; through-silicon via configuration; Arrays; Estimation; Piezoresistance; Stress; Three dimensional displays; Through-silicon vias; Transistors;
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011
Conference_Location :
Grenoble
Print_ISBN :
978-1-61284-208-0
DOI :
10.1109/DATE.2011.5763088
