A Low-Latency, Energy-Efficient L1 Cache Based on a Self-Timed Pipeline

Author

Trudeau, L.C. ; Gagnon, G. ; Gagnon, F. ; Thibeault, C. ; Awad, T. ; Morrissey, D.

Author_Institution

Dept. de Genie Electr., Ecole de Technol. Super., Montreal, QC, Canada

fYear

2015

fDate

4-6 May 2015

Firstpage

17

Lastpage

18

Abstract

The design of a low latency, energy-efficient self timed L1 cache is presented. The pipeline integrates Octasic´s token-based architecture and a two-phase handshake protocol derived from Click elements. Only standard flip-flops are used as state-holding elements for the pipeline control and data path. Simulations and post-layout static timing analysis were based on a commercial 28nm bulk process. Power analysis indicates a 20% improvement in energy efficiency when compared to the previous synchronous cache for the same throughput and area.

Keywords

cache storage; pipeline processing; power aware computing; protocols; Octasic token-based architecture; click elements; energy efficiency; energy-efficient self-timed L1 cache; low-latency energy-efficient L1 cache; pipeline control; post-layout static timing analysis; power analysis; self-timed pipeline; state-holding elements; synchronous cache; two-phase handshake protocol; Computer architecture; Delays; Pipelines; Program processors; Synchronization; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Asynchronous Circuits and Systems (ASYNC), 2015 21st IEEE International Symposium on

Conference_Location

Mountain View, CA

ISSN

1522-8681

Type

conf

DOI

10.1109/ASYNC.2015.11

Filename

7152685