The effect of parasitic bipolar transistor on the performance and reliability of scaled vertical power DMOSFETs

The parasitic bipolar transistor inherent in the silicided vertical double diffused MOSFET (DMOSFET) can greatly affect its performance and reliability. Scaled low-voltage power DMOSFETs with TiSi ₂ source contacts were reported and anomalous “kinks” in the output I-V characteristics were observed. It was shown that a high contact resistance of TiSi₂ contacts to the p-body diffusion caused the high output conductance. In this paper, a two-dimensional (2D) device simulator was used to investigate in detail the impact of the parasitic bipolar transistor on the static and dynamic switching characteristics of scaled silicided power MOSFETs. A mixed device and circuit simulator was used to determine the effect of bipolar parameters on the switching characteristics of devices under resistive and unclamped inductive switching (UIS) conditions. It is shown that a shallow surface-diffused p⁺ region is necessary to suppress the parasitic bipolar transistor-induced deleterious effects in developing the next generation of scaled power MOS technologies