DocumentCode :
3080269
Title :
Flow-based partitioning and position constraints in VLSI placement
Author :
Struzyna, Markus
Author_Institution :
Res. Inst. for Discrete Math., Univ. of Bonn, Bonn, Germany
fYear :
2011
fDate :
14-18 March 2011
Firstpage :
1
Lastpage :
6
Abstract :
This paper presents a new quadratic, partitioning-based placement algorithm which is able to handle non-convex and overlapping position constraints to subsets of cells, the movebounds. Our new flow-based partitioning (FBP) combines a global MinCostFlow model for computing directions with extremely fast and highly parallelizable local realization steps. Despite its global view, the size of the MinCostFlow instance is only linear in the number of partitioning regions and does not depend on the number of cells. We prove that our partitioning scheme finds a (fractional) solution for any given placement or decides in polynomial time that none exists. In practice, BonnPlace with FBP can place huge designs with almost 10 million cells and dozens of movebounds in 90 minutes of global placement. On instances with movebounds, the netlengths of our placements are more than 32% shorter than RQL´s and our tool is 9-20 times faster. Even without movebounds, the FBP improves the quality and runtime of BonnPlace significantly and our tool shows the currently best results on the latest placement benchmarks.
Keywords :
VLSI; integrated circuit interconnections; technology CAD (electronics); MinCostFlow instance; VLSI placement; flow-based partitioning; global placement; partitioning-based placement algorithm; position constraints; Benchmark testing; Computational modeling; Law; Partitioning algorithms; Runtime; Transportation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011
Conference_Location :
Grenoble
ISSN :
1530-1591
Print_ISBN :
978-1-61284-208-0
Type :
conf
DOI :
10.1109/DATE.2011.5763100
Filename :
5763100
Link To Document :
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