Title :
A Cluster Timing Algorithm for drift chambers readout electronics
Author :
Cappelli, L. ; Creti, P. ; Grancagnolo, F.
Author_Institution :
Lab. Naz. di Frascati, INFN, Frascati, Italy
Abstract :
A Cluster Timing Algorithm has been developed in order to store information coming from a 6 bits, 1 Gsample/s flash ADC. In particular the algorithm detects signal peaks and stores their amplitude and timing information. A Xilinx ML605 Evaluation Board, making use of a FPGA Virtex 6 core, has been employed in order to develop and test the VHDL code. The final goal is to develop a VME board capable of reading up to, at least, 4 ADC channels. The current algorithm, under continuous improvement, applied to simulated signals, satisfies the efficiency and timing constraints imposed. Code optimizations are currently under development.
Keywords :
analogue-digital conversion; field programmable gate arrays; hardware description languages; logic design; logic testing; readout electronics; signal detection; timing circuits; FPGA Virtex 6 core; VHDL code; VME board; Xilinx ML605 evaluation board; cluster timing algorithm; drift chamber readout electronics; flash ADC; information storage; signal peak detection; word length 6 bit; Ash; CMOS integrated circuits; Smoothing methods; Timing;
Conference_Titel :
Advances in Sensors and Interfaces (IWASI), 2011 4th IEEE International Workshop on
Conference_Location :
Savelletri di Fasano
Print_ISBN :
978-1-4577-0623-3
Electronic_ISBN :
978-1-4577-0622-6
DOI :
10.1109/IWASI.2011.6004683
