Linear transformation based efficient canonical signed digit multiplier using high speed and low power reversible logic

This paper proposes a reversible logic based canonical signed digit (CSD) multiplier design which is optimized further using sub expression elimination applied to linear transformation. It is examined that using linear transformation the number of gates required can be reduced which is efficient in terms of logic utilization, delay and power. Moreover reversible circuits have been intensively studied in recent years due to their applications in many areas, including quantum computing, nanotechnology and low-power design. In this research work the CMOS implementation of reversible logic comprehends the advantage that it is used for high speed and low power applications. Synthesis of reversible circuits differs significantly from the traditional logic synthesis. Common sub expression sharing as linear transformation reduces the number of add and shift operation which improves the logic utilization and delay. The proposed method in this paper shows 82% reduction in garbage outputs, 40% reduction in logical complexity,11% reduction in total number of gates used and an improvement in delay and device utilization is there in the linear transformation based 4-bit CSD multiplier as compared to existing logic.