A sub-1 V triple-threshold CMOS/SIMOX circuit for active power reduction

The triple-Vth CMOS/SIMOX circuit presented uses 0.25 /spl mu/m SIMOX devices with a small subthreshold swing to reduce leakage current in both the active and standby modes without speed degradation. A 16 b carry-lookahead adder uses the triple-Vth scheme. The logic gates in the critical carry-paths use low-Vth MOSFETs and other logic gates in non-critical paths are composed of medium-Vth MOSFETs. The ratio of the low-Vth MOSFET count to the medium-Vth MOSFET count is 1.3:1.0. Performance is compared with that of an all low-Vth adder using simulation. The delay times at 0.5 V are 5.2 ns for triple-Vth and 4.5 ns for all low-Vth. The active leakage power dissipations at 0.5 V are 38 /spl mu/W and 60 /spl mu/W respectively.