Title :
Multipliers Using Low Power Adder Cells Using 180nm Technology
Author :
Gupta, Jyoti ; Grover, Anuj ; Wadhwa, Garish Kumar ; Grover, Neeti
Author_Institution :
SBSSTC, Ferozepur, India
Abstract :
Multiplier is the most commonly used circuit in the digital devices. Multiplication is one of the basic functions used in digital signal processing. Most high performance DSP systems rely on hardware multiplication to achieve high data throughput. There are various types of multipliers available depending upon the application in which they are used. Full adder is the main block of power dissipation in multiplier. So reducing the power dissipation of full adder ultimately reduces the power dissipation of multiplier. In this article 8-bit multipliers based on Gate Diffusion Input (GDI) adder cells are compared using EDA Tanner, simulations are based on 180nm CMOS technology.
Keywords :
CMOS logic circuits; adders; digital signal processing chips; low-power electronics; multiplying circuits; CMOS technology; EDA tanner; GDI adder cells; digital devices; digital signal processing; gate diffusion input adder cells; hardware multiplication; high data throughput; high performance DSP systems; low power adder cells; multipliers; power dissipation; size 180 nm; Adders; Arrays; CMOS integrated circuits; Delays; Logic gates; Power demand; Transistors; Multiplier: Gate Diffusion Input;
Conference_Titel :
Computational and Business Intelligence (ISCBI), 2013 International Symposium on
Conference_Location :
New Delhi
Print_ISBN :
978-0-7695-5066-4
DOI :
10.1109/ISCBI.2013.8