DocumentCode :
3080724
Title :
Hardware to compute Walsh coefficients
Author :
Iguchi, Yukihiro ; Sasao, Tsutomu
Author_Institution :
Dept. of Comput. Sci., Meiji Univ., Kawasaki, Japan
fYear :
2005
fDate :
19-21 May 2005
Firstpage :
75
Lastpage :
81
Abstract :
This paper presents a method to compute a fragment of the Walsh coefficients of logic functions using hardware. First, it introduces the Walsh transformation tree, and shows a method to compute Walsh coefficients using the Walsh transformation tree. Next, it shows the hardware realization for the Walsh tree. The amount of hardware to compute a coefficient and the entire coefficients are O(2n) and O(n2·2n), respectively. FPGA implementations show their feasibility up to n=14. The FPGA realization is at least 1253 times faster than a software implementation on a microprocessor for n=14.
Keywords :
Boolean functions; Walsh functions; computational complexity; fast Fourier transforms; field programmable gate arrays; signal processing; trees (mathematics); Boolean function; FPGA implementation; Walsh coefficient; Walsh transformation tree; computational complexity; fast Fourier transform; logic function; signal processing; Application software; Computer science; Digital signal processing; Fast Fourier transforms; Fault diagnosis; Field programmable gate arrays; Hardware; Logic functions; Logic testing; Microprocessors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Multiple-Valued Logic, 2005. Proceedings. 35th International Symposium on
ISSN :
0195-623X
Print_ISBN :
0-7695-2336-6
Type :
conf
DOI :
10.1109/ISMVL.2005.19
Filename :
1423165
Link To Document :
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