Title : 
Multiple-valued logic-in-memory VLSI based on a floating-gate-MOS pass-transistor network
         
        
            Author : 
Hanyu, T. ; Teranishi, K. ; Kameyama, M.
         
        
            Author_Institution : 
Tohoku Univ., Sendai, Japan
         
        
        
        
        
        
            Abstract : 
A logic-in-memory structure, in which storage functions are distributed over a logic-circuit plane, is a solution to the communication bottleneck between memory and logic modules, one of the most serious problems in recent deep submicron VLSI systems technology. This logic-in-memory VLSI based on floating-gate MOS transistors merges storage and switching functions in a multiple-valued-input and binary-output combinational logic circuit that is useful for the realization of parallel arithmetic and logic circuits. The paper presents a general structure of a 4-valued-input and binary-output combinational logic circuit. It has two kinds of inputs, external and stored constant inputs. In the logic-in-memory VLSI, a large number of stored data are distributed in not only word-parallel but also in digit parallel manners.
         
        
            Keywords : 
multivalued logic circuits; combinational logic circuit; floating-gate-MOS pass-transistor network; multiple-valued logic-in-memory VLSI; parallel arithmetic; Arithmetic; EPROM; Logic circuits; MOSFETs; Nonvolatile memory; Performance evaluation; Switches; Switching circuits; Threshold voltage; Very large scale integration;
         
        
        
        
            Conference_Titel : 
Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International
         
        
            Conference_Location : 
San Francisco, CA, USA
         
        
        
            Print_ISBN : 
0-7803-4344-1
         
        
        
            DOI : 
10.1109/ISSCC.1998.672432