Title :
A 23.1µW 8 Bit 1.1 MS/s SAR ADC with counter based control logic
Author :
Boina, Srinivas ; Paily, Roy
Author_Institution :
Dept. of Electron. & Electr. Eng., Indian Inst. of Technol. Guwahati, Guwahati, India
Abstract :
This paper presents the implementation of Successive Approximation Architecture (SAR) based Analog to Digital Convertors (ADC). In order to reduce the power consumption and increase the speed, a double-tail latch type comparator is incorporated in the design. Charge redistribution DAC is used for area efficiency. A synchronous type SAR Logic with counter based controlled unit is proposed for faster operation. The structure is designed and simulated using 0.18 μm CMOS technology. The ADC consumes 23.1 μW power achieving a figure of merit of 119 fJ/conv-step and ENOB of 7.46.
Keywords :
CMOS logic circuits; analogue-digital conversion; counting circuits; digital-analogue conversion; flip-flops; power consumption; CMOS technology; ENOB; SAR ADC; SAR based analog to digital convertor; area efficiency; charge redistribution DAC; counter based control logic; counter based controlled unit; design; double-tail latch type comparator; figure of merit; power 23.1 muW; power consumption; size 0.18 mum; successive approximation architecture; synchronous type SAR logic; word length 8 bit; Approximation methods; Capacitors; Latches; Logic gates; Power demand; Radiation detectors; Registers; Analog-to-Digital Conversion; CMOS Technology; Charge Redistribution DAC; Successive Approximation Architecture; Synchronous;
Conference_Titel :
India Conference (INDICON), 2012 Annual IEEE
Conference_Location :
Kochi
Print_ISBN :
978-1-4673-2270-6
DOI :
10.1109/INDCON.2012.6420683
