DocumentCode
3081425
Title
MLP aware heterogeneous memory system
Author
Phadke, Sujay ; Narayanasamy, Satish
Author_Institution
Univ. of Michigan, Ann Arbor, MI, USA
fYear
2011
fDate
14-18 March 2011
Firstpage
1
Lastpage
6
Abstract
Main memory plays a critical role in a computer system´s performance and energy efficiency. Three key parameters define a main memory system´s efficiency: latency, bandwidth, and power. Current memory systems tries to balance all these three parameters to achieve reasonable efficiency for most programs. However, in a multi-core system, applications with various memory demands are simultaneously executed. This paper proposes a heterogeneous main memory with three different memory modules, where each module is heavily optimized for one the three parameters at the cost of compromising the other two. Based on the memory access characteristics of an application, the operating system allocates its pages in a memory module that satisfies its memory requirements. When compared to a homogeneous memory system, we demonstrate through cycle-accurate simulations that our design results in about 13.5% increase in system performance and a 20% improvement in memory power.
Keywords
DRAM chips; parallel memories; MLP aware heterogeneous memory system; computer system performance; energy efficiency; homogeneous memory system; main memory system; memory access characteristics; memory demands; memory level parallelism; memory modules; memory power; memory requirements; multicore system; operating system; Bandwidth; Benchmark testing; Memory management; Parallel processing; Prefetching; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011
Conference_Location
Grenoble
ISSN
1530-1591
Print_ISBN
978-1-61284-208-0
Type
conf
DOI
10.1109/DATE.2011.5763155
Filename
5763155
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