VLIW-processors under periodic real time constraints

This paper deals with the cyclo-static (periodic) scheduling of iterative instruction sequences on VLIW-processor architectures, in the case when the period is imposed (periodic real time constraints). This problem naturally arises when designing VLIW-processor architectures as I/O interfaces between cyclo-static-processor arrays and the external world. Three important mapping problems related to periodic real time constraints are discussed, depending on the VLIW-processor resource constraints and optimization criteria that are considered. Precise conditions under which there exist cycle-static schedules are formulated. Whenever possible, we present systematic and optimal mapping methodologies with polynomial solution time. The starting point is thereby a novel description of iterative instruction sequences in the form of generalized directed acyclic graphs (DAG´s). Finally, an innovative VLIW-processor architecture, called Extended Periodic Operation Model (EPOM) with distributed shift register file, which optimally fits into the mapping trajectory, is presented