DocumentCode :
3081948
Title :
The FPGA Implementation of High-Speed DS-CDMA Receiver
Author :
Diao Zhuo-zhi ; Wang Hao-Xian ; Shen Ying-hong ; Moa Xing-peng ; Liu Ai-ying
Author_Institution :
Dept. of Commun. Eng., Harbin Inst. of Technol. at Weihai, Weihai, China
fYear :
2010
fDate :
17-19 Sept. 2010
Firstpage :
751
Lastpage :
754
Abstract :
Nowadays, the higher frequency increases difficulty to implement full-digital receivers, a high-speed full-digital DS-CDMA receiver has been designed based on FPGA in the paper, meanwhile, traditional digital system is improved by adopting the idea of high-speed digital system, and the PN module is implemented in a new way, moreover, the effect of despread-demodulator for direct-sequence spread-spectrum system on high-speed and low-occupation system is introduced, also the method of omitting filter under certain conditions is given, in the end, the simulation and experiment results are presented.
Keywords :
code division multiple access; demodulators; field programmable gate arrays; filtering theory; radio receivers; spread spectrum communication; FPGA implementation; PN module; code division multiple access; despread-demodulator; direct-sequence spread-spectrum system; field programmable gate array; high-speed full-digital DS-CDMA receiver; omitting filter method; Clocks; Field programmable gate arrays; Generators; Hardware; Multiaccess communication; Receivers; Time frequency analysis; Digital DS-CDMA Receiver; FPGA; High-speed; VHDL;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Pervasive Computing Signal Processing and Applications (PCSPA), 2010 First International Conference on
Conference_Location :
Harbin
Print_ISBN :
978-1-4244-8043-2
Electronic_ISBN :
978-0-7695-4180-8
Type :
conf
DOI :
10.1109/PCSPA.2010.187
Filename :
5635583
Link To Document :
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