DocumentCode :
3082084
Title :
SAMURAI: An accurate method for modelling and simulating non-stationary Random Telegraph Noise in SRAMs
Author :
Aadithya, Karthik V. ; Demir, Alper ; Venugopalan, Sriramkumar ; Roychowdhury, Jaijeet
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA, USA
fYear :
2011
fDate :
14-18 March 2011
Firstpage :
1
Lastpage :
6
Abstract :
In latest CMOS technologies, Random Telegraph Noise (RTN) has emerged as an important challenge for SRAM design. Due to rapidly shrinking device sizes and heightened variability, analytical approaches are no longer applicable for characterising the circuit-level impact of non-stationary RTN. Accordingly, this paper presents SAMURAI, a computational method for accurate, trap-level, non-stationary analysis of RTN in SRAMs. The core of SAMURAI is a technique called Markov Uniformisation, which extends stochastic simulation ideas from the biological community and applies them to generate realistic traces of non-stationary RTN in SRAM cells. To the best of our knowledge, SAMURAI is the first computational approach that employs detailed trap-level stochastic RTN generation models to obtain accurate traces of non-stationary RTN at the circuit level. We have also developed a methodology that integrates SAMURAI and SPICE to achieve a simulation-driven approach to RTN characterisation in SRAM cells under (a) arbitrary trap populations, and (b) arbitrarily time-varying bias conditions. Our implementation of this methodology demonstrates that SAMURAI is capable of accurately predicting non-stationary RTN effects such as write errors in SRAM cells.
Keywords :
CMOS memory circuits; Markov processes; SPICE; SRAM chips; random noise; write-once storage; CMOS technology; Markov uniformisation; SAMURAI core; SPICE; SRAM cells; arbitrary trap populations; biological community; circuit level; circuit-level impact; nonstationary analysis; nonstationary random telegraph noise; stochastic simulation; time-varying bias conditions; trap-level stochastic RTN generation; write errors; Computational modeling; Electron traps; Integrated circuit modeling; Markov processes; Random access memory; SPICE; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011
Conference_Location :
Grenoble
ISSN :
1530-1591
Print_ISBN :
978-1-61284-208-0
Type :
conf
DOI :
10.1109/DATE.2011.5763183
Filename :
5763183
Link To Document :
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