Design and implementation of a decimation filter for hearing aid applications

In this paper we deal with the design and implementation of a decimation filter used for hearing aid applications. We implement the decimation filter using the canonic signed digit (CSD) representation. Each digital filter structure is simulated using Matlab, and its complete architecture is captured using DSP Blockset and Simulink. The filter has been implemented on Xilinx FPGA using Virtex-2 technology. The resulting architecture is hardware efficient and consumes less power compared to conventional decimation filters. Compared to the comb-FIR-FIR architecture, the designed decimation filter architecture contributes to a hardware saving of 69%; in addition, it reduces the power dissipation by 83%, respectively.