Title :
DFT for supply current testing to detect open defects at interconnects in 3D ICs
Author :
Suenaga, Shunichiro ; Hashizume, Masaki ; Yotsuyanagi, Hiroyuki ; Shyue-Kung Lu ; Roth, Zvi
Author_Institution :
Univ. of Tokushima, Tokushima, Japan
Abstract :
In this paper, a Design-for-Testability method is proposed to detect an open defect occurring at an interconnect between dies in a 3D IC. The open defect is detected by means of a supply current flowing whenever a time-varying voltage signal is provided to the targeted interconnect as a test input stimulus. Feasibility of the test method is examined by targeted experiments and circuit simulations. It is shown that an open defect in a testable designed IC is capable of being detected by measuring the supply current of the IC.
Keywords :
design for testability; integrated circuit interconnections; integrated circuit testing; three-dimensional integrated circuits; 3D integrated circuit; DFT; design for testability method; integrated circuit interconnection; open defect detection; supply current testing; Integrated circuit interconnections; Integrated circuit modeling; Inverters; Logic gates; Prototypes; Three-dimensional displays; 3D IC Test; Design-for-Testability; interconnect test; open defect; supply current test;
Conference_Titel :
Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2013 IEEE
Conference_Location :
Nara
Print_ISBN :
978-1-4799-2313-7
DOI :
10.1109/EDAPS.2013.6724389
