Three-dimensional packaging structure for 3D-NoC

In this paper, we propose a novel three-dimensional (3D) packaging structure for a network-on-chip (NoC) based a 3D system-on-chip (SoC). Our SiP is implemented by vertically connecting two homogeneous SoCs through an organic interposer; that is, two homogeneous SoCs are bonded face-to-face above and below the organic interposer. NoCs have routing capability that can communicate with each other even if opposing nodes are connected to different node pins, which enables high-speed communication between SoCs using low voltage and current. As the power supply and external I/O pins are implemented via the organic interposer, we performed simulations to assess power integrity (PI) and signal integrity (SI) compared to a conventional package. To assess vertical communication performance as a 3D package, we simulated high-speed characteristics using the organic interposer and through silicon vias (TSVs), and confirmed the superior performance of the organic interposer.