A new level converter for low-power applications

In dual supply voltage circuits, when connecting a V_DDL-supplied circuit to a V_DDH-supplied circuit, it is necessary to insert a level converter at each low-to-high boundary as the interface to prevent static current. In this paper, we propose a new low-power level converter circuit technique, called Symmetrical Dual Cascode Voltage Switch (SDCVS), which will reduce the contention problem that existed in the conventional Dual Cascode Voltage Switch (DCVS) design. These level converters are simulated for different capacitive loads and operating conditions using the HSPICE parameters of a 0.35 μm digital CMOS technology. The HSPICE simulations show that the proposed circuit can achieve 50% power reduction and 60% speed increase over those of the existing technique. In addition, the proposed level converter can operate at different values of V_DDL ranging from 1.2 V to 5 V. Hence, the proposed technique is suited for low power design without degrading performance