An FPGA implementation and performance evaluation of the seed block cipher

An FPGA implementation of the 128-bit SEED block cipher is presented in this paper. The proposed architecture achieves high-speed with little hardware resources using feedback logic and inner pipeline with negative edge-triggered registers. In this way, the delay of the critical path is reduced, without increasing the latency of cipher execution. The proposed implementation reaches a data throughput of 369.6 Mbps at 46.2 MHz clock frequency. The design was coded using VHDL language and for the hardware implementation, the Xilinx Spartan-3A FPGA device was used.