DocumentCode :
3082641
Title :
Integration of formal specification into the standard ASIC design flow
Author :
Haas, Werner ; Gossens, Stefan ; Heinkel, Ulrich
Author_Institution :
Inst. for Comput. Aided Circuit Design, Erlangen-Nurnberg Univ., Erlangen, Germany
fYear :
2002
fDate :
2002
Firstpage :
189
Lastpage :
194
Abstract :
This paper presents our approach to leverage formal methods in an industrial design environment by closing the gap between the specification and design phases. We achieve this goal by deriving behavioural VHDL models from a formal system specification in tabular form that is easily accessible to mathematical analysis.
Keywords :
application specific integrated circuits; circuit CAD; formal specification; hardware description languages; behavioural VHDL models; formal specification; industrial design environment; mathematical analysis; standard ASIC design flow; tabular form; Application specific integrated circuits; Circuit synthesis; Computer industry; Computer science; Electronics industry; Formal specifications; Mathematical analysis; Mathematical model; Natural languages; Systems engineering and theory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Assurance Systems Engineering, 2002. Proceedings. 7th IEEE International Symposium on
ISSN :
1530-2059
Print_ISBN :
0-7695-1769-2
Type :
conf
DOI :
10.1109/HASE.2002.1173122
Filename :
1173122
Link To Document :
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