Many-module redundancy implementation of mono instruction set computers for 3D optical FPGAs

Demand for programmable devices for space applications is increasing day-by-day to support hardware repair functions, hardware update functions, and hardware acceleration for space systems. An optically reconfigurable gate array (ORGA) has been developed as a robust multi-context field programmable gate array that is quite suitable for such space applications. The ORGA can be reconfigured using corrupt configuration data with nanosecond-order reconfiguration speed. Currently, we also propose a mono-instruction set computer architecture exploiting the high-speed dynamic reconfiguration. Using the mono-instruction set computer architecture, many-module redundancy over triple module redundancy (TMR) can be realized. This paper presents one demonstration result of a mono-instruction set computer and its robust capabilities.