Mono-instruction set computer architecture on a 3D optically reconfigurable gate array

Currently, three-dimensional VLSI technologies are being developed. However, by increasing the number of layers of TSV or stacking layers, the production difficulty of VLSI is increased. Therefore, optically reconfigurable gate arrays (ORGAs) have been developed to realize high-speed dynamic reconfiguration. The ORGA consists of a holographic memory, a programmable gate array, and a laser array. An ORGA can store large amounts of circuit information inside a holographic memory. The circuit information can be programmed dynamically onto an ORGA´s programmable gate array in nanosecond-order. The ORGA allows high-speed dynamic reconfiguration. If the high-speed dynamic reconfiguration can be used for the implementation of processors, then the processor performance can be increased. The implementation technique is called a mono-instruction set computer (MISC) architecture. This paper presents a demonstration result of a high-performance MISC architecture that fully exploits the high-speed programmability of an ORGA.