DocumentCode
3083114
Title
Multiple LDPC decoder of very low bit-error rate
Author
Tsatsaragkos, I. ; Kanistras, N. ; Paliouras, V.
Author_Institution
Electr. & Comput. Eng. Dept., Univ. of Patras, Patras, Greece
fYear
2011
fDate
6-8 July 2011
Firstpage
1
Lastpage
6
Abstract
The error correcting capability of LDPC based systems at low noise levels is often dominated by the so-called error floor, a region in the BER vs. noise level plot, where BER reduction slows down as the noise level decreases. The error floor behavior is commonly attributed to the sub-optimality of iterative decoding algorithms on graphs with cycles, which become trapped to local minimum solutions. Trapping of the decoder depends on several factors, including the decoding algorithm. A particular received word that is not decoded by a certain algorithm may be decoded successfully by a different algorithm. The proposed Multiple Decoder exploits this diverse behavior, by decoding a particular received word with N different algorithms, composing an LDPC decoder that achieves very low BER in the error floor region of operation, less iterations and higher throughput than the equivalent single decoder system.
Keywords
error correction codes; error statistics; iterative decoding; parity check codes; LDPC decoder; bit error rate; error floor region; iterative decoding; noise level plot; Bit error rate; Charge carrier processes; Decoding; Hardware; Iterative decoding; Noise level; LDPC decoding; error floor; low BER; multiple decoder; soft-decoding;
fLanguage
English
Publisher
ieee
Conference_Titel
Digital Signal Processing (DSP), 2011 17th International Conference on
Conference_Location
Corfu
ISSN
Pending
Print_ISBN
978-1-4577-0273-0
Type
conf
DOI
10.1109/ICDSP.2011.6004951
Filename
6004951
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