DocumentCode :
3083185
Title :
Analog circuit reliability in sub-32 nanometer CMOS: Analysis and mitigation
Author :
Gielen, Georges ; Maricau, Elie ; De Wit, Pieter
Author_Institution :
ESAT-MICAS, K.U. Leuven, Leuven, Belgium
fYear :
2011
fDate :
14-18 March 2011
Firstpage :
1
Lastpage :
6
Abstract :
The paper discusses reliability threats and opportunities for analog circuit design in high-k sub-32 nanometer technologies. Compared to older SiO2 or SiON based technologies, transistor reliability is found to be worse in high-k nodes due to larger oxide electric fields, the severely aggravated PBTI effect and increased time-dependent variability. Conventional reliability margins, based on accelerated stress measurements on individual transistors, are no longer sufficient nor adequate for analog circuit design. As a means to find more accurate, circuit-dependent reliability margins, advanced degradation effect models are reviewed and an efficient method for stochastic circuit reliability simulation is discussed. Also, an example 6-bit 32nm current-steering digital-to-analog converter is studied. Experiments demonstrate how the proposed simulation tool, combined with novel design techniques, can provide an up to 89% better area-power product of the analog part of the circuit under study, while still guaranteeing a 99.7% yield over a lifetime of 5 years.
Keywords :
CMOS analogue integrated circuits; circuit simulation; digital-analogue conversion; integrated circuit design; integrated circuit reliability; integrated circuit yield; nanoelectronics; transistor circuits; PBTI effect; accelerated stress measurements; advanced degradation effect models; analog circuit design; analog circuit reliability; area-power product; circuit under study; circuit-dependent reliability margins; conventional reliability margins; current-steering digital-to-analog converter; design techniques; high-k nanometer technology; high-k nodes; individual transistors; nanometer CMOS; oxide electric fields; reliability threats; simulation tool; stochastic circuit reliability simulation; time-dependent variability; transistor reliability; CMOS integrated circuits; High K dielectric materials; Integrated circuit modeling; Integrated circuit reliability; Reliability engineering; Transistors; Aging; Design for Reliability; Failure-Resilience; HBD; High-k CMOS; Hot Carriers; NBTI; PBTI; SBD; TDDB;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011
Conference_Location :
Grenoble
ISSN :
1530-1591
Print_ISBN :
978-1-61284-208-0
Type :
conf
DOI :
10.1109/DATE.2011.5763239
Filename :
5763239
Link To Document :
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