DocumentCode :
3083220
Title :
Accelerating Yield Ramp through Real-Time Testing
Author :
Taneja, Sanjiv
Author_Institution :
Vice President and General Manager of Test Technology Cadence
fYear :
2007
fDate :
8-11 July 2007
Firstpage :
11
Lastpage :
11
Abstract :
With the increasing need for design specific yield optimization in nanometer technologies, it is becoming increasingly important to accelerate the identification of the root cause of systematic defects under very tight test cost constraints. This talk will give a high level overview of addressing these demanding challenges through a mix of cross-disciplinary EDA technologies spanning scan diagnostics, DFT, ATPG, BIST, DFM and real-time monitoring from ATE systems.
Keywords :
automatic test pattern generation; built-in self test; design for testability; nanotechnology; ATE systems; ATPG; BIST; DFM; DFT; EDA technologies spanning scan diagnostics; accelerating yield ramp; design specific yield optimization; nanometer technologies; real-time monitoring; real-time testing; Automatic test pattern generation; Built-in self-test; Constraint optimization; Cost function; Design for manufacture; Design optimization; Electronic design automation and methodology; Life estimation; Real time systems; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
On-Line Testing Symposium, 2007. IOLTS 07. 13th IEEE International
Conference_Location :
Crete
Print_ISBN :
0-7695-2918-6
Type :
conf
DOI :
10.1109/IOLTS.2007.12
Filename :
4274814
Link To Document :
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