DocumentCode
3083378
Title
Reversed nested Miller compensation with current follower
Author
Mita, R. ; Palumbo, Gaetano ; Pennisi, S.
Author_Institution
Dipartimento Elettrico Elettronico e Sistemistico, Catania Univ., Italy
Volume
1
fYear
2001
fDate
6-9 May 2001
Firstpage
308
Abstract
The reversed nested-Miller compensation technique is reviewed by using a simple design-oriented approach. A single current follower is also exploited to provide right-half-plane zero removal while allowing wide band and preserving output swing. Thanks to the small compensation capacitors employed, the approach is suited for integration. SPICE simulations, using the parameters of a 0.8-μm CMOS process, are in excellent agreement with theoretical derivations
Keywords
CMOS analogue integrated circuits; SPICE; cascade networks; circuit simulation; compensation; integrated circuit design; operational amplifiers; 0.8 micron; CMOS process; OTAs; SPICE simulations; current follower; design-oriented approach; output swing; reversed nested Miller compensation; right-half-plane zero removal; Bandwidth; CMOS process; Capacitors; Circuits; Equations; Frequency; SPICE; Semiconductor device modeling; Transconductance; Wideband;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location
Sydney, NSW
Print_ISBN
0-7803-6685-9
Type
conf
DOI
10.1109/ISCAS.2001.921854
Filename
921854
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