DocumentCode :
308347
Title :
Steps to Petaflops computing: a hybrid technology multithreaded architecture
Author :
Sterling, Thomas L. ; Gao, Guang ; Likharev, Konstantin K. ; Kogge, Peter M. ; MacDonald, Michael J.
Author_Institution :
California Inst. of Technol., Pasadena, CA, USA
Volume :
2
fYear :
1997
fDate :
1-8 Feb 1997
Firstpage :
41
Abstract :
The paradigm of massively parallel processing and message-passing concurrent processes has culminated in the Federal HPCC goal of achieving teraflops-scale computing. Detailed studies of important applications have demonstrated that critical needs of mission-drives agencies and major scientific and engineering challenges require substantially more computing capability i.e., petaflops-scale computing. The first workshop on Enabling Technologies for Peta(FL)ops Computing in February, 1996 provided a first examination of the potential opportunities and challenges to the future achievement of petaflops computing systems. Subsequent workshops have addressed hardware, architecture, and software issues. The Petaflops Architecture WorkShop (PAWS) in April, 1996 concentrated on alternative architecture approaches to petaflops computer systems development. The Petaflops System Software Summer Study (PetaSoft) in June, 1996 focused on the fundamental problem of system software, its requirements, and approaches to supporting petaflops computing. An important element in both workshops was a set of sponsored studies in near-petaflops architecture initiated by NSF in cooperation with NASA and DARPA. The eight studies proposed a number of approaches to petaflops systems architecture including software. Parallelism, bandwidth, and latency were considered the principal challenges to effective petaflops computing and required solutions involving all levels of hardware, software, and algorithms techniques. This paper provides a perspective of some of the key questions, critical issues, findings, and recommendations pertinent to petaflops architecture from the two petaflops systems workshops
Keywords :
parallel architectures; CMOS; DARPA; Federal HPCC goal; NASA; bandwidth; engineering applications; holographic memories; hybrid technology multithreaded architecture; massively parallel processing; message-passing concurrent processes; mission-drives agencies; petaflops computing; scientific applications; superconductor RSFQ logic; teraflops-scale computing; Bandwidth; Computer architecture; Concurrent computing; Delay; Hardware; NASA; Parallel processing; Plasma welding; Software systems; System software;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Aerospace Conference, 1997. Proceedings., IEEE
Conference_Location :
Snowmass at Aspen, CO
Print_ISBN :
0-7803-3741-7
Type :
conf
DOI :
10.1109/AERO.1997.577615
Filename :
577615
Link To Document :
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