Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design

In the future sub 45 nm regime, uncertainties would be way too high to be handled with existing worst-case design techniques without incurring significant penalties in terms of area/delay/energy. As a result, reliability becomes a great threat to the design of reliable complex digital systems-on-chip (SoC) implementations. This will require the development of novel reliability models at all three levels, namely device, circuit and system level. They should be capable of capturing the impact of the application functionality on the system as well as new design paradigms for embedded system design in order to build reliable systems using technology which will be largely unpredictable in nature. A shift toward technology-aware design solutions will be required to keep designing successful systems in future aggressively scaled technologies.