Title :
Standard design flows of logic LSIs in Japanese universities and VDEC
Author_Institution :
VDEC, Tokyo Univ.
Abstract :
We describe two pilot activities of VDEC (VLSI Design and Education Center) in 1998; testing new implementation technologies and development of IPs. In the former project we tested Hitachi´s 0.35 μm technology, where 10 major universities participated and several kinds of design methods and libraries were tried and evaluated. In the latter project, we aimed to encourage IP design and distribution in Japanese universities, where 6 major universities participated. The designed and measured results will be opened in several levels of abstraction; hard IP macro blocks, soft IPs and analog modules
Keywords :
VLSI; circuit CAD; electronic engineering education; integrated circuit design; logic design; 0.35 mum; Hitachi technology; IP design; Japanese universities; VLSI Design and Education Center; analog modules; hard IP macro blocks; logic LSIS; soft IP; standard design flows; Educational institutions; Large scale integration; Logic design;
Conference_Titel :
Microelectronic Systems Education, 1999. MSE'99. IEEE International Conference on
Conference_Location :
Arlington, VA
Print_ISBN :
0-7695-0312-8
DOI :
10.1109/MSE.1999.787011
